Microprocessore AEC-Q100 Microchip DSPIC33CK256MP502-I/2N, 16bit, 100MHz, UQFN 28 Pin
- Codice RS:
- 179-3985
- Codice costruttore:
- DSPIC33CK256MP502-I/2N
- Costruttore:
- Microchip
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- Codice RS:
- 179-3985
- Codice costruttore:
- DSPIC33CK256MP502-I/2N
- Costruttore:
- Microchip
Specifiche
Documentazione Tecnica
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Seleziona tutto | Attributo | Valore |
|---|---|---|
| Marchio | Microchip | |
| Famiglia | dsPIC | |
| Larghezza del bus dati | 16bit | |
| Frequenza massima | 100MHz | |
| Tensione di I/O | 3 → 3.6V | |
| Tecnologia di produzione | CMOS | |
| Tipo di montaggio | Montaggio superficiale | |
| Tipo di package | UQFN | |
| Numero pin | 28 | |
| Tensione di alimentazione operativa tipica | 3,6 V (max) | |
| Dimensioni | 6 x 6 x 0.5mm | |
| Standard per uso automobilistico | AEC-Q100 | |
| Minima temperatura operativa | -40 °C | |
| Massima temperatura operativa | +85 °C | |
| Seleziona tutto | ||
|---|---|---|
Marchio Microchip | ||
Famiglia dsPIC | ||
Larghezza del bus dati 16bit | ||
Frequenza massima 100MHz | ||
Tensione di I/O 3 → 3.6V | ||
Tecnologia di produzione CMOS | ||
Tipo di montaggio Montaggio superficiale | ||
Tipo di package UQFN | ||
Numero pin 28 | ||
Tensione di alimentazione operativa tipica 3,6 V (max) | ||
Dimensioni 6 x 6 x 0.5mm | ||
Standard per uso automobilistico AEC-Q100 | ||
Minima temperatura operativa -40 °C | ||
Massima temperatura operativa +85 °C | ||
Microchips dsPIC33CK family of digital signal controllers (DSCs) features a single 100 MIPS 16-bit dsPIC® DSC core with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors.
3.0V to 3.6V, -40ºC to +125ºC, DC to 100 MIPS
dsPIC33CK DSC Core:
Modified Harvard architecture with 16-bit data and 24-bit instructions
Code efficient (C and Assembly) CPU architecture designed for real-time applications
16 16-bit working registers
4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
Single-cycle, mixed-sign 32-bit MUL
Fast 6-cycle hardware 32/16 and 16/16 DIV
Dual 40-bit fixed point Accumulators (ACC) for DSP operations
Single-cycle MAC/MPY with dual data fetch and result write-back
Zero overhead looping support
dsPIC33CK DSC Core:
Modified Harvard architecture with 16-bit data and 24-bit instructions
Code efficient (C and Assembly) CPU architecture designed for real-time applications
16 16-bit working registers
4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
Single-cycle, mixed-sign 32-bit MUL
Fast 6-cycle hardware 32/16 and 16/16 DIV
Dual 40-bit fixed point Accumulators (ACC) for DSP operations
Single-cycle MAC/MPY with dual data fetch and result write-back
Zero overhead looping support
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